module ysyx_22040213_outDataSel( //can be regard as  mul to one for register
//	input w_en,
//	input lm_en,
//	input jumpr_en,
//	input jump_en,
	input clint_hit,
	input [3:0] RegisterWritedata_en,
	input [63:0] clint_rdata,
	input [63:0] csr_src1,
	input [63:0] mrdata,//data from memory
	input [63:0] adata, //data from alu
	input [63:0] pc_link, 
	//should add in 3 from nextpc
	output [63:0] wdata
);
	wire [4:0] RW_en;
	assign RW_en[3:0] = RegisterWritedata_en;
	assign RW_en[4]   = RegisterWritedata_en[2] && clint_hit;
	MuxKey #(5, 5, 64) i0 (wdata, RW_en, {
		5'b01001, csr_src1,
		5'b00100, mrdata,
		5'b00010, pc_link,
		5'b00001, adata,
		5'b10100, clint_rdata
		});

endmodule
